VLSI design services
Front-end, back-end, verification and test — delivered as a turnkey block, a dedicated team, or embedded engineers.
Our practices
Each practice can run standalone or as part of an end-to-end RTL-to-GDSII engagement.
RTL Design & Synthesis
Micro-architecture, synthesisable RTL, lint/CDC clean-up and constraint-driven synthesis.
Physical Design (PD)
Floorplan through route and signoff — block and full-chip implementation with timing closure.
Static Timing Analysis (STA)
Constraint development, multi-corner multi-mode closure and signoff-quality timing ECOs.
Design Verification (DV)
UVM environments, coverage-driven verification, assertions and gate-level simulation.
Design for Test (DFT)
Scan architecture, compression, ATPG, MBIST and JTAG integration with coverage signoff.
End-to-end flow coverage
Where each practice sits in the implementation flow.
1. RTL Design & Synthesis
Micro-architecture, RTL coding, lint and CDC, constraints, synthesis, formal equivalence. Details →
2. Design Verification
Testbench architecture, UVM environments, coverage closure, assertions, gate-level simulation. Details →
3. Design for Test
Scan architecture, compression, ATPG, MBIST, JTAG, test coverage signoff. Details →
4. Physical Design
Floorplan, power plan, placement, CTS, route, physical verification, signoff. Details →
5. Static Timing Analysis
Constraint development, MMMC setup, setup/hold closure, timing ECOs, signoff. Details →
Engagement models
Fixed-scope block
Defined deliverables and signoff criteria, milestone-based. Best when the specification is stable.
Dedicated team
Monthly team of named engineers under your technical direction. Best for multi-quarter programmes.
Embedded engineers
Individuals joining your team and your process. Best for covering a peak or a specific skills gap.
Not sure which practice you need?
Describe the problem — a block that will not close, a verification backlog, a test coverage gap — and we will tell you what it takes.