Physical Design
Netlist to GDSII — floorplan, power, placement, CTS, route and physical signoff, with timing closed at every stage.
What we deliver
We take a synthesised netlist, constraints and a PDK, and return a routed, physically verified database with the full signoff report set. Blocks, subsystems or full-chip integration — hard macro hardening through top-level assembly.
Flow stages we own
Floorplanning
Die and core sizing, macro placement and orientation, pin and port planning, blockage and halo strategy, region and partition definition, congestion-driven iteration.
Power planning
Power grid design and stripe planning, ring and via strategy, power switch and always-on domain handling for multi-voltage designs, and early IR-drop feasibility.
Placement
Timing- and congestion-driven placement, scan reordering, useful-skew and datapath optimisation, high-fanout net synthesis, and pre-CTS timing convergence.
Clock tree synthesis
Clock architecture and skew targets, CTS with insertion-delay and skew budgeting, clock gating integration, multi-corner clock balancing and post-CTS optimisation.
Routing
Global and detail routing, layer and via optimisation, signal-integrity-aware routing, antenna and DRC fixing, and post-route optimisation.
Physical verification
DRC, LVS and antenna signoff, metal fill and density, ERC, and the LEF/GDS/abstract deliverables downstream teams need.
Signoff we close against
Timing
Multi-corner multi-mode setup and hold closure, correlated between the implementation tool and the signoff timer, with physically aware timing ECOs.
Power & IR
Static and dynamic IR-drop analysis, electromigration checks on the grid, and power recovery passes that do not cost timing.
Physical & reliability
DRC / LVS clean to the foundry deck, antenna and density rules, and crosstalk / noise analysis fed back into route.
Typical deliverables
- Routed DEF and final GDSII
- Post-route netlist, SPEF and SDF
- MMMC timing reports with the closure summary
- DRC, LVS, antenna and density signoff reports
- IR-drop and EM analysis reports
- Block abstract (LEF), timing model (.lib) and integration notes
- Documented, reproducible run scripts and a QoR trend log
Have a block that will not close?
Tell us the node, the utilisation, the clock targets and where it is stuck. We will tell you what we would try first.