Careers at Gnavin
We hire engineers who want to own real silicon problems — and we tell you honestly what the work involves.
Roles we hire for
Openings vary with programme demand. If your skills match a practice below, send your CV even when nothing is listed — we keep strong profiles on file.
Physical Design Engineer
Floorplan through route and signoff. You should be comfortable with at least one industry implementation tool and with reading your own timing reports.
STA Engineer
Constraint development, MMMC closure and timing ECOs. Strong SDC understanding matters more than tool familiarity.
RTL Design Engineer
Micro-architecture and synthesisable SystemVerilog/Verilog, with lint, CDC and synthesis awareness.
Design Verification Engineer
UVM environment development, coverage-driven verification and assertions. SystemVerilog depth expected.
DFT Engineer
Scan and compression architecture, ATPG, MBIST and JTAG, plus the gate-level simulation to prove it.
Internships & freshers
Structured entry routes for strong VLSI graduates. Expect a technical screen on fundamentals rather than on tool button-clicking.
What we look for
Fundamentals first
Digital design, CMOS basics, timing and testability. Tools can be taught inside a quarter; the fundamentals underneath them cannot.
Debug instinct
The engineers who do well here are the ones who chase a violation to its actual root cause instead of applying the first waiver that makes it disappear.
Written clarity
Our deliverables include documents. Being able to explain a decision in writing is part of the job, not an extra.
How to apply
Email your CV to srikar@gnavin.in with the role in the subject line. Please include the tools and process nodes you have worked with, the blocks or projects you contributed to, and your notice period.
We read every application. If your profile fits a current or upcoming programme we will reach out to arrange a technical discussion.
Ready to apply?
Send your CV to srikar@gnavin.in with the role in the subject line.