Design for Test
Scan architecture, compression, ATPG and memory test — inserted early enough that it does not cost you timing.
What we deliver
DFT decides your test cost and your defect coverage, and it is cheapest to get right before physical design starts. We define the test architecture, insert and verify it, generate and simulate the patterns, and hand over coverage numbers you can sign off against.
Scope of work
Test architecture
DFT strategy and coverage targets, scan chain count and partitioning, compression ratio selection, test clock and reset planning, and pin budgeting agreed with the package and PD teams.
Insertion & integration
Scan insertion and stitching, compression logic, JTAG/IEEE 1149.1 boundary scan, MBIST for embedded memories, and hierarchical DFT integration at the top level.
Pattern generation
ATPG for stuck-at, transition and path-delay faults, pattern count and test-time optimisation, and pattern validation by gate-level simulation with timing.
Where DFT meets the rest of the flow
With RTL
Testability rule checking on the RTL, fixing uncontrollable clocks and resets and unscannable structures before insertion — not after.
With physical design
Scan chain reordering during placement, shift-mode and capture-mode timing constraints, and test-mode power and IR considerations for the shift pattern.
With STA
Constraints for shift, capture and at-speed modes included in the MMMC matrix, so test modes close alongside functional modes rather than after them.
Typical deliverables
- DFT architecture document with coverage targets
- Scan-inserted netlist and DFT integration scripts
- DRC / testability rule-check reports
- ATPG patterns in the required formats with fault coverage reports
- Gate-level simulation results validating the patterns
- Test-mode constraints for implementation and timing
- MBIST and JTAG integration and verification reports
Planning DFT for a new design?
The earlier we are involved, the less it costs in area, timing and test time. Tell us where you are in the schedule.